2020OFC論文閱讀 T4D.2 FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON
FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON 貝爾實驗室的文章 部署在FPGA上的固定節點的神經網絡均衡器接收機靈敏度性能要優於MLSE均衡器在下行50G PON場景下。 色散產生了接收信號的非線性 神經網絡結構 OOK信號 全連接 ReLU函數 輸出層節點數爲2的時候，不是on
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