Vivado dubug core被刪除解決方法（The debug hub core was not detected, Dropping logic with cellname:'xxx'）
情景描述： 使用Vivado 2017.4書寫Verilog代碼，並且創建debug core進行信號抓取。添加完debug core併成功Run Implementaion,在IMPLEMENTATION的結構圖中可以看到相應的ila_core和hub都已經建立。在生成bit文件的時候出現warning告知debug core被丟掉了，因爲沒有在設備上找到相應的內容，警告截圖如下： 雖然bit文
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