報錯一：app
WARNING: [Labtools 27-3361] The debug hub core was not detected.less
Resolution:ide
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.ui
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.debug
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).orm
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file(s) E:/fpga/mt100_v2/nand_x8/v2/mt100_v2/mt100_v2.runs/impl_1/mt100_v2_wrapper.ltx.server
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file(s) have 3 ILA core(s) and 0 VIO core(s).blog
Resolution:ci
1. Reprogram device with the correct programming file and associated probes file(s) OR資源
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.
報錯二：
ERROR: [Labtools 27-3312] Data read from hw_ila [hw_ila_1] is corrupted. Unable to upload waveform.
首先要了解什麼是 debug hub core？
a debug core hub (dbg_hub) is automatically inserted into the synthesized design netlist to provide connectivity between the new ILA core and the JTAG scan chain.
debug hub 負責將一個或幾個ILA與JTAG鏈接起來。JTAG指令下發以及抓取的波形數據回傳到screen都要經過它。
（參考 p133 - ug908-vivado-programming-debugging.pdf）
就像這個，把3個ILA連到JTAG上。
從warning的提示來看，一、這個hub的clock不正常；或者二、兩個參數不匹配（通常參數都是01沒問題，能夠在properties中查到）。
那麼重點是clk爲何不對？
Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
我遇到過兩種狀況，致使clock不正常的。
一、clock線連上了，可是這個wire上卻沒有clock波形，由於zynq的ps端沒有啓動配置，因此沒有任何clock到pl端；
二、咱們設置的clock頻率跟JTAG仿真器的不匹配。重點來講這個。
在以前正常的project中，dbg_hub的clk都是鏈接在clk_out1（40mhz）上，此次連到了clk_800k，爲何鏈接變了？ 頻率低了有什麼問題？
在p35-ug908上有指明 「The JTAG chain is as fast as the slowest device in the chain.」
dbg_hub上面一共掛了3個device，clock分別是40mhz、20mhz、800khz，因此才連到了這個最低的800k上面。
在xilinx的forum上有個QA，Data read from hw_ila is corrupted 。其中提到 「Can you please check whether your JTAG frequency is lower than ILA clock frequency? It is recommended to keep the JTAG frequency half or less than half of ILA clock frequency.」
雖而後半句，推薦一半或更低的freq沒有在ug908上找到依據，可是jtag比ILA低這個是原理性的。The JTAG chain is as fast as the slowest device in the chain.也是這個意思。
ERROR: [Xicom 50-38] xicom: No trigger mark in any sample in window: 0.
ERROR: [Xicom 50-41] Waveform data read from ILA core is corrupted (user chain=1, slave index=0).
Resolution:
1) Ensure that the clock signal connected to the debug core and/or debug hub is clean and free-running.
2) Ensure that the clock connected to the debug core and/or debug hub meets all timing constraints.
3) Ensure that the clock connected to debug core and/or debug hub is faster than the JTAG clock frequency.
ERROR: [Xicom 50-38] xicom: Error during interpreting trace readback data
ERROR: [Labtools 27-3176] hw_server failed during internal command.
Resolution: Check that the hw_server is running and the hardware connectivity to the target
此次報錯已經說明的很清楚了，ILA和HUB的clock必定要比JTAG的高！
p35上還有一段，」a default JTAG clock frequency that is 15 MHz for the Digilent cable connection and 6 MHz for the USB cable connection.「
也就是說，我用的這個USB-JTAG仿真器跑的默認頻率是6mhz。這個6mhz比40mhz和20mhz低能夠work，但明顯高於800k的。
那麼根因已經很清楚了，報錯的project中debug hub這個中間鏈接件的clock比 jtag仿真器的低，正確的應該是確保jtag是最低的！
很明顯，解決辦法有兩個。
一、把jtag仿真器的頻率降下去。
Program and Debug --> Open hardware manager--> Open Target --> Open new target （先關掉以前打開的hardware）
能夠選750khz，比800k低。實測確承認行，並且明顯刷新波形界面的速度慢下來了，這是確定的。
二、把debug hub的頻率升上去。
在setup debug中產生的ILA相關的XDC約束文件最後一段，把 connect_debug_port dbg_hub/clk [get_nets u_ila_2_clk_800k] 改爲參考 u_ila_0_clk_out1，40mhz。實測也OK。
是否能夠把頻率設置成800k？ set_property C_CLK_INPUT_FREQ_HZ 800000 [get_debug_cores dbg_hub]
答案是不行的，這個明顯是設置dbg_hub的，默認300mhz，實際仍是由 u_ila_2_clk_800k 實際決定的。還得改jtag的Hz。
延伸，ILA及DEBUG模塊佔用fpga資源，也會影響用戶邏輯timing。因此通常系統默認連lowest的那個clock，或者把 C_ENABLE_CLK_DIVIDER true。
參考TCL指令：
get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]