【電路】差分接口互連（一）

 對LVDS接口的研究

 

　　LVDS Output 

　　

 

VOS – Offset voltage: the common-mode voltage of the LVDS output。

Output Common-Mode voltage 共模輸出電壓VOCM，在driver端叫作 offset voltage VOS，典型值是1.2V。

考慮到共模和差模電壓的偏移，輸出兩端電壓能夠達到max 1.6V（1.375v + 450/2mv），min 0.9V（1.125v - 450/2mv）。

 

　　LVDS Input

VCC is always higher than R IN+ and R IN− voltage. R IN− and R IN+ are allowed to have a voltage range of −0.2 V to VCC − VID/2.

However, to be compliant with ac specifications, the common voltage range is 0.1 V to 2.3 V.

The ADN4662 differential line receiver is capable of receiving signals of 100 mV over a ±1 V common-mode range centered around 1.2 V.

This relates to the typical driver offset voltage value of 1.2 V. The signal originating from the driver is centered around 1.2 V and may shift ±1 V around this center point.

This ±1 V shifting may be caused by a difference in the ground potential of the driver and receiver, the common-mode effect of coupled noise, or both.

　　Wide input common mode range

 

設定芯片供電參數

　　輸出接口要求

The board power supply (VTRM) is the voltage used to terminate the comparator outputs on the IC.

Setting VTRM to +1.2V makes the high-speed digital I/Os compatible with LVDS levels.

計算芯片輸出接口的 Vocm = （CTV + CTV-400mv）/2 = CTV - 200mv；其必須符合後級

FPGA的輸入共模範圍Vicm = 0.3v~1.425v，即0.3v < Vocm < 1.425v，得出0.5V < CTV < 1.625V。

 

　　輸入接口要求

The high-speed digital inputs (DATA0/NDATA0,RCV0/NRCV0, DATA1/NDATA1, and RCV1/NRCV1) are intended for use with a high-speed differential signal source such as LVDS, LVPECL, ECL, etc.

    

該片子內部有100歐姆終端電阻，很是適合匹配LVDS輸出接口，並且單端電平及差分擺幅都很寬。

前級FPGA的標準LVDS Vocm = 1.25v，Vpp = 350m，獲得1.075V < Vo <  1.425V;

手冊標出最大Voh=1.675V，考慮到信號線與BV之間的esd管，則BV必須大於上面的值，BV>=1.675V，

 

取CTV=+1.625V，BV=+2.5V/+1.8V。

參考：

LVDS Owner's Manual Design Guide, 4th Edition

AN-1177: LVDS和M-LVDS電路實施指南 (Rev. 0)

SN65LVDS四、DS10BR150、ADN466一、ADN4662