【電路】差分接口互連（二）

•  LVDS接口類型

 一種是HR bank的LVDS_25，Vcco=2.5V，也就是一般說的LVDS接口。

The LVDS_25 I/O standard is only available in the HR I/O banks. It requires a VCCO to be powered at 2.5V for outputs and for inputs when the optional internal differential termination is implemented (DIFF_TERM = TRUE).

 一種是HP bank的LVDS，Vcco=1.8V

The LVDS I/O standard is only available in the HP I/O banks. It requires a VCCO to be powered at 1.8V for outputs and for inputs when the optional internal differential termination is implemented (DIFF_TERM = TRUE).

這句話的意思是，做爲LVDS的輸出或者做爲輸入且選擇了內部終端電阻，那麼VCCO的電壓必須設置成1.8V（或者HR的2.5V）。

It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs).

However, these criteria must be met:（ug471_7Series_SelectIO， P92）

• The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value).

• The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet

• The differential signals at the input pins meet the VIDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the specific device family data sheet

• For HR I/O banks in bidirectional configuration, internal differential termination is always used.

可是，若是隻做爲輸入則不受Vcco=1.8V/2.5V限制，由於輸入信號並不關心Vcco輸出電壓，只參考VREF電壓（可選VREF_pin或者原語的 Internal_VREF）。

通常上級2.5V LVDS輸出到1.5V bank是能夠直連的，DC能夠知足要求。可是想輸入到DDR3L 1.35V的bank就須要注意些：

　　一、內部終端電阻不能選，必須外接；二、前級輸出的DC特性要知足1.35V輸入要求。

 可是每一個bank都有對應的VREF（外接電阻或者內部原語），能夠將輸入偏置在Vcco/2，因此做爲輸入也是沒有問題的。

• AC-couples and DC-biases the input signals

最保險的作法是採用上面的AC耦合電路，不用關心前級的直流量，只有交流信號經過，而後在輸出端配置一個VCCO/2偏置電壓。

 

總結，一般說的LVDS是2.5V的供電接口，但HP也提供1.8V的供電接口，由於DC參數徹底知足。在2.5V/1.8V的bank中，能夠任意配置Lvds Ourput Input，可是在其餘Vcco供電bank中，就只能謹慎有條件的配置成Lvds Input，不能做爲Lvds Output。