K60時鐘分析

轉載：https://blog.csdn.net/hcx25909/article/details/7164650

1.飛思卡爾K60時鐘系統

    

    飛思卡爾K60時鐘系統如上圖所示，能夠發現器件的源時鐘源一共有4個：

    ①內部參考時鐘源，包括 Fast IRC和 slow IRC (IRC--Internal Reference Clock)

    ②外部參考時鐘源，只一個EXTAL管腳做爲時鐘輸入，這個能夠使用有源晶體振盪器來實現

    ③外部晶體諧振器，使用EXTAL和XTAL兩個管腳來輸入

    ④外部32K RTC 諧振器，用於實時時鐘的時鐘輸入

    在圖中能夠看到，要爲系統提供時鐘信號，關鍵是要最終生成 MCGOUTCLK 輸出。MCGOUTCLK 再通過分頻即可以提供Core/system clocks、Bus clock、FlexBus clock和Flash clock。MCGOUTCLK 的產生有3個途徑:

    ①由內部參考時鐘源 Fast IRC 直接提供，這個時鐘源集成在芯片的內部（包括Slow IRC），頻率是2M

    ②由 FLL 或者 PLL 模塊來提供

    ③由外部時鐘來直接提供，包括外部參考時鐘源（1個管腳輸入）、外部晶體諧振器經內部OSC logic產生的XTAL_CLK 和 RTC OSC logic 的時鐘輸出。

 

    通常狀況下，MCGOUTCLK 是由PLL或者FLL倍頻來產生的，飛思卡爾官方的例程最終是由PLL模塊來產生。圖中能夠看到PLL模塊的時鐘輸入是OSCCLK或者RTC OSC logic。個人板子之外部參考時鐘源提供PLL時鐘，最終經PLL倍頻產生MCGOUTCLK。即 EXTAL-->PLL模塊-->MCGOUTCLK.

 

2.關於時鐘模式

 

 

   從圖中能夠看到，該芯片一共包含8種工做時鐘模式，外加Stop模式。系統在RESET後直接進入默認的FEI模式。圖中，F--FLL、P--PLL、E--Enable或者EXTAL(外部時鐘)、B--Bypass(旁路)、I--Internal(內部參考時鐘)、L--Low Power.

·FLL 啓用、內部參考時鐘（FEI）, 內部參考時鐘提供FLL的時鐘，FLL驅動MCGOUT

·FLL 啓用、外部參考時鐘（FEE）, 外部參考時鐘提供FLL的時鐘，FLL驅動MCGOUT

·FLL 旁路、內部參考時鐘（FBI），FLL雖然在運做但由內部時鐘參考源驅動MCGOUT 

·FLL 旁路、外部參考時鐘（FBE），FLL雖然在運做但由外部時鐘參考源驅動MCGOUT 

·PLL 旁路、外部參考時鐘（PBE），PLL雖然在運做但由外部時鐘參考源驅動MCGOUT 

·PLL 啓用、外部參考時鐘（PEE），外部參考時鐘提供PLL的時鐘，PLL驅動MCGOUT

·BLPI FLL和PLL都禁用，內部時鐘參考源驅動MCGOUT

·BLPE FLL和PLL都禁用，外部時鐘參考源驅動MCGOUT

 

    因爲系統在重啓後默認進入FEI模式，咱們的目標是要跳到PEE模式，因此要涉及到模式的轉化。圖中由FEI到PEE是不能直接跳轉的，必須經由其餘模式來轉換。

 

 

3.官方具體的例子

來源於飛思卡爾官方\src\drivers\mcg\mcg.c

unsigned char pll_init(unsigned char clk_option, unsigned char crystal_val)
{
  unsigned char pll_freq;

  if (clk_option > 3) {return 0;} //return 0 if one of the available options is not selected
  if (crystal_val > 15) {return 1;} // return 1 if one of the available crystal options is not available
//This assumes that the MCG is in default FEI mode out of reset.

// First move to FBE mode
#if (defined(K60_CLK) || defined(ASB817))
     MCG_C2 = 0;
#else
// Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
    MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
#endif

// after initialization of oscillator release latched state of oscillator and GPIO
    SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
    LLWU_CS |= LLWU_CS_ACKISO_MASK;

// Select external oscilator and Reference Divider and clear IREFS to start ext osc
// CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
  MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);

  /* if we aren't using an osc input we don't need to wait for the osc to init */
#if (!defined(K60_CLK) && !defined(ASB817))
    while (!(MCG_S & MCG_S_OSCINIT_MASK)){}; // wait for oscillator to initialize
#endif

  while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear

  while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk

// Now in FBE

#if (defined(K60_CLK))
   //MCG_C5 = MCG_C5_PRDIV(0x18);
   MCG_C5 = MCG_C5_PRDIV(0x18); //基頻2M 外部時鐘源是50M時, 50/25=2M
#else
// Configure PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=5
// The crystal frequency is used to select the PRDIV value. Only even frequency crystals are supported
// that will produce a 2MHz reference clock to the PLL.
  MCG_C5 = MCG_C5_PRDIV(crystal_val); // Set PLL ref divider to match the crystal used
#endif

  // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
  MCG_C6 = 0x0;
// Select the PLL VCO divider and system clock dividers depending on clocking option
  switch (clk_option) {
    case 0:
      // Set system options dividers
      //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
      set_sys_dividers(0,0,0,1);
      // Set the VCO divider and enable the PLL for 50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
      MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
      pll_freq = 50;
      break;
   case 1:
      // Set system options dividers
      //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
     set_sys_dividers(0,1,1,3);
      // Set the VCO divider and enable the PLL for 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
      MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
      pll_freq = 100;
      break;
    case 2:
      // Set system options dividers
      //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
      set_sys_dividers(0,1,1,3);
      // Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
      MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
      pll_freq = 96;
      break;
   case 3:
      // Set system options dividers
      //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
      set_sys_dividers(0,0,0,1);
      // Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
      MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
      pll_freq = 48;
      break;
  }
  while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set

  while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set

// Now running PBE Mode

// Transition into PEE by setting CLKS to 0
// CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
  MCG_C1 &= ~MCG_C1_CLKS_MASK;

// Wait for clock status bits to update
  while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};

// Now running PEE Mode

return pll_freq;
} //pll_init