Verilog HDL學習_1：分頻器/PWM的實現

（一）參考學習資料

 

（二）實際操做

1. 相關變量計算：

	First Initial		Second Initial
Upper case	H		X
ASCII (Dec)	72		88
Lengths of the pulse
Mu	Mu_1	2.5*105	Mu_2	2.5*105
k : mu	ku_1 : mu_1	1.2812:3.7188	ku_2 : mu_2	1.3438:3.6562
nu	nu_1	18	nu_2	18
Ku	Ku_1	64060	Ku_2	67190
Lower case	h		x
ASCII (Dec)	104		120
Lengths of the pulse
Ml	Ml_1	2.5*105	Ml_2	2.5*105
k : ml	kl_1 : ml_1	1.4063:3.5937	k : ml_2	1.4688:3.5312
nl	nl_1	18	nl_2	18
Kl	Kl_1	70315	Kl_2	73440

 

 

2. 初版：

 1 module Assignment2(rst, CP, Z);
 2     input CP;
 3     input rst;  //1 for upper & 0 for lower
 4     
 5     reg turn = 0;
 6     reg [1:0] cyc = 0; //use for the number of cycles
 7     
 8     //constant parameters
 9     parameter k = 100, n = 8, K = 100;
10     parameter KK = K-1;
11     
12     //take parameters according to rst input
13     reg [7:0] M;
14     reg [7:0] MM;
15     reg [4:0] m;
16     //output of the lautch
17     output Z;
18     reg Z;
19     
20     
21     //parameters of upper case
22     parameter [7:0] Mu [0:1] = {128, 134};
23     parameter [4:0] mu [0:1] = {28, 34}; 
24     //parameter Ku_1 = k*Mu_1/(k+mu_1);
25     parameter [7:0] MMu [0:1] = {127, 133};
26     //Parameter []KKu_1 = Ku_1-1;
27     

34     //parameters of lower case
35     parameter [7:0] Ml [0:1] = {141, 147};
36     parameter [4:0] ml [0:1] = {41, 47}; 
37     parameter [7:0] MMl [0:1] = {127, 133};
38 
39     //Check rst to determine upper or lower.
40     //check the number of turn to determine the first two or the second.
41     always@(posedge CP)
42     begin
43         if(rst)
44             begin
45             M <= turn ? Mu[1]:Mu[0];
46             m <= turn ? mu[1]:mu[0];
47             MM <= turn ? MMu[1]:MMu[0];
48             end
49         else if(!rst)
50             begin
51             M <= turn ? Ml[1]:Ml[0];
52             m <= turn ? ml[1]:ml[0];
53             MM <= turn ? MMl[1]:MMl[0];
54             end
55     end
56     
57     //Latch
58     reg [n-1:0] Q = 0;
59     wire ld, cz;
60     assign ld = Q>=MM;
61     assign cz = (Q<KK)|ld;
62     
63     always@(posedge CP) 
64     begin
65         {Q,Z} <= {ld?0:Q+1, cz};
66         cyc = ld ? cyc+1 : cyc;
67         
68         if(cyc == 2) 
69             begin
70             turn <= 1;
71             cyc <= 0;
72             end
73         else begin
74             turn <= 0;
75             end
76     end
77         
78         
79 endmodule

 

• 出現問題1：

解決方案：將以下部分的變量類型由reg改成了input，系統沒有再次崩潰。

12     //take parameters according to rst input
13     reg [7:0] M;
14     reg [7:0] MM;
15     reg [4:0] m;
16     //output of the lautch
17     output Z;
18     reg Z;

緣由：不明

補充：reg變量不可按位賦值，在二維數組中的賦值應爲下圖第一種方法。

// Correct
M <=Mu[1];

// Wrong
M <=Mu[1][7:0];

 

• 出現問題2：vwf文件仿真時，M沒有成功賦值

解決方案：修正了對reg寬度的定義。

補充：

1. Verilog中reg類型的寬度是自定義的，若無定義則默認爲1bit。reg的寬度影響變量的取值，若賦值超出reg的範圍，不會產生Error，reg變量的最大值將被默認爲reg寬度。修改變量時應注意該變量的取值範圍。

2. reg變量只能存儲整數，容許的運算爲加減乘除，若要實現浮點數須要以此爲基礎構建相關專門的模塊。

 

3. 第二版：

 1 module Assignment2(rst, CP, Z, K);
 2     input CP;
 3     input rst;  //1 for upper & 0 for lower
 4     
 5     reg turn = 0; 
 6     //use to determine whether the first group of pulses or the second one
 7     reg [3:0] cyc = 0; 
 8     //use for the number of pulses in one 'turn'
 9     
10     ////constant parameters
11     parameter n = 18, M = 250000;
12     parameter MM = M-1;
13     
14     ////take parameters according to rst input
15     output [n-1:0] K;
16     reg [n-1:0] K = 0;
17 
18     ////output of the lautch
19     output Z;
20     reg Z;
21     
22     ////parameters of upper case
23     parameter Ku_1 = 64060; 
24     parameter Ku_2 = 67190; 
25 
26     ////parameters of lower case
27     parameter Kl_1 = 70315; 
28     parameter Kl_2 = 73440; 
29     
30     ////Latch
31     reg [n-1:0] Q;
32     wire ld, cz;
33     assign ld = Q>=MM;
34     assign cz = (Q<K-1)|ld;
35     
36     always@(posedge CP) 
37     begin
38         ////Check rst to determine upper or lower.
39         ////check the number of turn to determine the first two or the second.    
40         case(rst)
41         0: begin
42                 if(turn)K <= Kl_2;
43                 else if(!turn)K <= Kl_1;
44                 else K <= 100;
45             end
46         1: begin
47                 if(turn)K <= Ku_2;
48                 else if(!turn)K <= Ku_1;
49                 else K <= 200;
50             end
51         default: K <= 9999999;
52         endcase
53         
54         ////renew the state and output clock.
55         {Q,Z} <= {ld?0:Q+1, cz};
56         cyc = ld ? cyc+1 : cyc;
57         
58         ////1 cyc represent a pulse
59         ////2 cycles cause an increment in turn
60         ////4 cycles for an entire loop 
61         if(cyc == 2) 
62             begin
63             turn <= 1;
64             end
65         else if(cyc==4 && turn==1)
66             begin
67             turn <= 0;
68             cyc <= 0;
69             end
70 
71     end
72         
73 endmodule

 

• 仿真結果：//K的取值有修改。

• 補充：在Z的第一個輸出前有一小段空白期，測量爲微秒級，第一個輸出仍爲5ms。感受應該不影響時鐘的使用，但沒有通過硬件檢測。