cocotb-cocotb是一個基於協程的協同仿真庫，用於用Python編寫VHDL和Verilog測試臺。-Chris Higgs, Stuart Hodgson Installation U...

cocotb-cocotb是一個基於協程的協同仿真庫，用於用Python編寫VHDL和Verilog測試臺。-Chris Higgs, Stuart Hodgson

發佈:2020-12-23 13:35:13.969124

做者:Chris Higgs, Stuart Hodgson

做者郵箱:

首頁:https://docs.cocotb.org

文檔:None

下載連接

cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.

• Read the documentation
• Get involved:
  • Raise a bug / request an enhancement (Requires a GitHub account)
  • Join the mailing list
  • Join the Gitter chat room

Installation

Cocotb requires:

• Python 3.5+
• A C++11 compiler
• An HDL simulator (such as Icarus Verilog)

After installing these dependencies, the latest stable version of cocotb can be installed with pip.

pip install cocotb

!!! Windows Users !!! See here for installation instructions.

For more details on installation, including prerequisites, see the documentation.

For detail on how to install the development version of cocotb, see the lastest documentation.

Usage

As a first trivial introduction to cocotb, the following example "tests" a flip-flop.

First, we need a hardware design which we can test. For this example, create a file dff.sv with SystemVerilog code for a simple D flip-flop. You could also use any other language a cocotb-supported simulator understands, e.g. VHDL.

// dff.sv

`timescale 1us/1ns

module dff (
    output logic q,
    input logic clk, d
);

always @(posedge clk) begin
    q <= d;
end

endmodule

An example of a simple randomized cocotb testbench:

# test_dff.py

import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge

@cocotb.test()
async def test_dff_simple(dut):
    """ Test that d propagates to q """

    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
    cocotb.fork(clock.start())  # Start the clock

    for i in range(10):
        val = random.randint(0, 1)
        dut.d <= val  # Assign the random value val to the input port d
        await FallingEdge(dut.clk)
        assert dut.q == val, "output q was incorrect on the {}th cycle".format(i)

A simple Makefile:

# Makefile

TOPLEVEL_LANG = verilog
VERILOG_SOURCES = $(shell pwd)/dff.sv
TOPLEVEL = dff
MODULE = test_dff

include $(shell cocotb-config --makefiles)/Makefile.sim

In order to run the test with Icarus Verilog, execute:

make SIM=icarus

For more information please see the cocotb documentation and the wiki.

Tutorials, examples and related projects

• Endian Swapper tutorial
• Ping using TUN/TAP tutorial
• Cocotb based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
• Functional Coverage and Constrained Randomization Extensions for Cocotb
• UVM 1.2 port to Python

For more related resources please check the wiki and the list of projects depending on cocotb.

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