systemverilog中Configuration的用法詳解

SystemVerilog中Configuration的用法

1. Config

configuration是一套用來描述設計中實例來源的一套顯式規則， 它的規則以下：

2. 語法

config < config_name >;
design [< library >.]< cell >
default liblist [{< libraries >}];
cell [< library >.]< cell > liblist [{< libraries >}];
cell [< library >.]< cell > use [< library >.]< cell >[:config];
instance < full_hierarchical_path > liblist [{< libraries >}];
instance < full_hierarchical_path > use [< library >.]< cell >[:config];
endconfig

3. example

lib.map :

library rtlLib *.v; // matches all files in the current directory with a .v suffix
library gateLib ./*.vg; // matches all files in the current directory with a .vg suffix

config cfg1; // specify rtl adder for top.a1, gate-level adder for top.a2
    design rtlLib.top;
    default liblist rtlLib;
    instance top.a2 liblist gateLib; 
endconfig

上面就是一個最簡單的例子，經過configuration來選擇對於某個instance使用哪一個module的實現

4. 講解

一個configuration的基本元素包含：

• config/endconfig
• design
• default + liblist : 這兩個一般是一塊兒出現來指定默認搜索庫
• instance + liblist： 綁定某個instance到某個庫

高級元素包含：
use : 只用於instance和cell後面來指定精確的lib和cell

config bot;
    design lib1.bot;
    default liblist lib1 lib2;
    instance bot.a1 liblist lib3;
endconfig
config top;
    design lib1.top;
    default liblist lib2 lib1;
    instance top.bot use lib1.bot:config;
    instance top.bot.a1 liblist lib4;   // ERROR - cannot set liblist for top.bot.a1 from this config
    cell adder use gateLib.adder;
endconfig

5. 參數設置

adder.sv

module adder #(parameter ID = "id",
W = 8,
D = 512)
(...);
...
$display("ID = %s, W = %d, D = %d", ID, W, D);
...
endmodule: adder

top.sv

module top (...);
parameter WIDTH = 16;
adder a1 (...); 
endmodule 

module top4 ();
parameter S = 16;
adder a1 #(.ID("a1"))(...);
adder a2 #(.ID("a2"))(...);
adder a3 #(.ID("a3"))(...);
adder a4 #(.ID("a4"))(...);
endmodule

Case 1

config cfgl;
design rtlLib.top;
instance top use #(.WIDTH(32));
instance top.a1 use #(.W(top.WIDTH));
endconfig

輸出結果是：

ID = id, W=32, D = 512

Case 2

config cfg2;
localparam S = 24
design rtlLib.top4;
instance top4.a1 use #(.W(top4.S));
instance top4.a2 use #(.W(S));
endconfig

輸出結果是：

ID = a1, W=16, D = 512
ID = a2, W=24, D = 512
ID = a3, W=8, D = 512
ID = a4, W=8, D = 512

Case 3

module top5 (...);
parameter WIDTH = 64, DEPTH = 1024, ID = "A1"; 
adder a1 #(.ID(ID), .W(WIDTH), .D(DEPTH))(...);
endmodule

輸出結果是：

ID = A1, W=64, D = 1024

Case 4

config cfg3;
design rtlLib.top5;
instance top5.a1 use #(.W()); // set only parameter W back to its default 
endconfig

輸出結果是：

ID = A1, W=8, D = 1024

Case 5

config cfg4;
design rtlLib.top;
instance top.a1 use #(); // set all parameters in instance a1 
// back to their defaults
endconfig

輸出結果是：

ID = id, W=8, D = 512

Case 6

test.sv

module test;
...
top8 t(...);
defparam t.WIDTH = 64;
defparam t.a1.W = 16;
...
endmodule

top8.sv

module top8 (...);
parameter WIDTH = 32;
adder a1 #(.ID("a1")) (...);
adder a2 #(.ID("a2"),.W(WIDTH))(...);
endmodule

adder.sv

module adder #(parameter ID = "id",
W = 8,
D = 512)
(...);
...
$display("ID = %s, W = %d, D = %d", ID, W, D);
...
endmodule

cfg6.sv

config cfg6;
design rtlLib.test;
instance test.t use #(.WIDTH(48));
endconfig

輸出結果是：

ID = a1, W=16, D = 512
ID = a2, W=48, D = 512

總結

若是設計中有聲明同樣，實現不同的兩個模塊被不一樣的模塊使用，這個時候Configuration是很是必要的。雖然各個工具也有各自的方法，但它們畢竟不通用，沒法被其餘工具使用。因此最好的方法仍是使用Configuration.