verilog HDL 進擊之路

Verilog 進擊之路 - 夯實基礎第一節之結構化設計

       隨着數字電路設計的複雜化和專業化，傳統的電路設計逐漸沒落，Verilog HDL逐漸走入歷史舞臺。好多人並非不會Verilog，而是缺少細緻的瞭解。最近一直在看 A Guide to Digital Deisgn and Synthesis  這本書，感受許多的疑點獲得解決，正好分享出來共勉。

　　對設計者來說，最重要的是如何實現設計和優化設計。以下是 A typical design flow. 

1. specifications are written first. specificitions 簡要描述了設計電路的function, interface, overall architecture.
2. a behavioral description 來分析設計電路的function, peoformance,compliance to standards and high-level issues.
3. behavioral description converted to RTL description. 
4. RTL description converted to gate-level netlist by logic synthesis tools.
5. The netlist is input to an automatic place and route tool, which creats a layout.

　　在進行Verilog design時，必須follow design methodology and basic hierarchical modeling.

         1.Design methodology: a  combination of top-down and bottom-up.  先構建設計的架構，進行top_level and sub_block的邏輯關係實現，而後在sub_block中build leaf cell and optimized circuits in cell，從而實現top and bottom 的同時設計. 

         2. Basic hierarchical modeling: a module is the basic buliding block in verilog. 共有四個design level能夠使用。behavioral level   dataflow level   gate level  switch level.

　　  3. Test bench include stimulus/monitor and design blocks,搭建仿真環境也要follow the design rules.

 

　　本次重點是瞭解一個verilog design的層次化結構是如何展開的，下節將會闡述做爲 basic block 的 module framework是如何實現的.