LPC43xx Dual-core or Multi-core configuration and JLink Debug

時間 2019-11-05

標籤 lpc43xx lpc dual core multi configuration jlink debug 简体版

原文原文鏈接

Test access port (TAP)

JTAG defines a TAP (Test access port).git

The TAP is a general-purpose port that can provide access to many test support functions built into a component.session

It is composed as a minimum of the three input connections (TDI, TCK, TMS) and one output connection (TDO).app

An optional fourth input connection (nTRST) provides for asynchronous initialization of the test logic.less

JTAG的接口是一種特殊的4/5個接腳接口連到芯片上，因此在電路版上的不少芯片能夠將他們的JTAG接腳async

經過Daisy Chain的方式連在一塊兒，而且Probe只需鏈接到一個「JTAG端口」就能夠訪問一塊印刷電路板上的全部IC。ide

這些鏈接引腳是：測試

TDI（測試數據輸入）
TDO（測試數據輸出）
TCK（測試時鐘）
TMS（測試模式選擇）
TRST（測試復位）可選。

Test Clock Input (TCK)fetch

TCK爲TAP的操做提供了一個獨立的、基本的時鐘信號，TAP的全部操做都是經過這個時鐘信號來驅動的。ui

Test Mode Selection Input(TMS)this

TMS信號用來控制TAP狀態機的轉換。經過TMS信號，能夠控制TAP在不一樣的狀態間相互轉換。TMS信號在TCK的上升沿有效。

Test Data Input(TDI)

TDI是數據輸入的接口。全部要輸入到特定寄存器的數據都是經過TDI輸入端口串行輸入的（由TCK驅動）。

Test Data Output(TDO)

TDO是數據輸出的接口。全部要從特定的寄存器中輸出的數據都是經過TDO輸出端口串行輸出的（由TCK驅動）。

Test Reset Input(TRST)

TRST能夠用來對TAP Controller進行復位(初始化)。

不過這個信號接口在IEEE 1149.1標準裏是可選的，由於經過TMS也能夠對TAP Controller進行復位(初始化)操做。

Data registers

JTAG requires at least two data registers to be present:

the bypass and the boundary-scan register.

Other registers are allowed but are not obligatory.

Bypass data register :

A single-bit register that passes information from TDI to TDO.

Boundary-scan data register :

A test data register which allows the testing of board interconnections, access to input and output of components when testing their system logic and so on.

Instruction register

The instruction register holds the current instruction and its content is used by the TAP controller to decide which test to perform or which data register to access.

It consist of at least two shift-register cells.

Determining values for scan chain configuration

When do I need to configure the scan chain?

If only one device is connected to the scan chain, the default configuration can be used.

In other cases, J-Link / J-Trace may succeed in automatically recognizing the devices on the scan chain,

but whether this is possible depends on the devices present on the scan chain.

How do I configure the scan chain?

2 values need to be known:

The position of the target device in the scan chain.
The total number of bits in the instruction registers of the devices before the target device (IR len).

The position can usually be seen in the schematic; the IR len can be found in the manual supplied by the manufacturers of the others devices.
ARM7/ARM9 have an IR len of four.

Sample configurations

The diagram below shows a scan chain configuration sample with 2 devices connected to the JTAG port.

Examples

The following table shows a few sample configurations with 1,2 and 3 devices in different configurations.

The target device is marked in blue.

Multi-core debugging

J-Link / J-Trace is able to debug multiple cores on one target system connected to the same scan chain.

Configuring and using this feature is described in this section.

How multi-core debugging works

Multi-core debugging requires multiple debuggers or multiple instances of the same debugger.

Two or more debuggers can use the same J-Link / J-Trace simultaneously.

Configuring a debugger to work with a core in a multi-core environment does not require special settings.

All that is required is proper setup of the scan chain for each debugger.

This enables J-Link / J-Trace to debug more than one core on a target at the same time.

The following figure shows a host, debugging two CPU cores with two instances of the same debugger.

Both debuggers share the same physical connection.

The core to debug is selected through the JTAG-settings as described below.

The picture below shows the configuration for the first CPU core on your target.

The following dialog box shows the configuration for the second ARM core on your target.

Example:

LPC43xx JTAG Debug Notes

The LPC43xx is a multi-core microcontroller implementing an ARM Cortex-M4 and one or two ARM Cortex-M0 cores.

All cores have access to the complete memory map.

The ARM Cortex-M4 is used as them main processor.

One ARM Cortex-M0core (M0APP) can be used as co-processor to off-load the ARM Cortex-M4 and to perform serial I/O tasks.

The other ARM Cortex-M0 core (M0SUB) - if available - is typically used to control the SGPIO and SPI peripherals.

This core (M0SUB) is connected through a bridge to the main Cortex-M4 processor.

1.7.1 ARM Cortex-M4 processor

The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses
as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching.

The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions.
A hardware floating-point processor is integrated in the core.

The processor includes an NVIC with up to 53 interrupts.

The ARM Cortex-M4 is implemented with a Memory Protection Unit supporting eight regions,
a hardware Floating Point Unit (FPU), debugging features, and a system tick timer.

1.7.2 ARM Cortex-M0 co-processors

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low-power consumption.

The ARM Cortex-M0 co-processor uses a 3-stage pipeline von-Neumann architecture
and a small but powerful instruction set providing high-end processing hardware.

The co-processor incorporates an NVIC with up to 32 interrupts.

Both ARM Cortex-M0 <M0APP and M0SUB> cores are implemented in the same way supporting a 32-cycle multiplier and debug features.

A system tick timer is not included.

The ARM Cortex-M0APP processor is available on all LPC43xx parts.

The ARM Cortex-M0SUB subsystem core is only available on parts LPC4370.

The ARM Cortex-M4 processor is used after reset as the top-level system controller.

After power-up or wake-up from Deep power-down mode, the M0 core or cores remain in reset until the reset is released by software running on the M4 core.

Then, the M4 can communicate with one or both M0 cores through shared memory space and interrupts.

JTAG TAP Identification

Debug and trace functions are integrated into the ARM Cortex-M4.

Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions.

The ARM Cortex-M4 is configured to support up to 8 breakpoints and 4 watch points.

The ARM Cortex-M0 coprocessor supports JTAG debug.

A standard ARM Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex-M0 cores separately or both cores simultaneously.

Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the RGU block.

LPC4350_DebugCortexM4.JLinkScript

/*********************************************************************
*               SEGGER MICROCONTROLLER GmbH & Co KG                  *
*       Solutions for real time microcontroller applications         *
**********************************************************************
*                                                                    *
*       (c) 2011  SEGGER Microcontroller GmbH & Co KG                *
*                                                                    *
*       www.segger.com     Support: support@segger.com               *
*                                                                    *
**********************************************************************
----------------------------------------------------------------------
Purpose : J-Link script file for NXP LPC4350 device.
          The NXP LPC4350 is a Cortex-M4 based device which has an
          additional Cortex-M0 core inside which can be enabled.
          This script puts the M0 in the JTAG chain if necessary.
          Releasing the M0 from reset etc. needs to be done on the debugger side.
---------------------------END-OF-HEADER------------------------------
*/

/*********************************************************************
*
*       _StoreSelDP
*/
void _StoreSelDP(void) {
  JTAG_StoreIR(0xA);  // DPACC command
  JTAG_StoreClocks(1);
}

/*********************************************************************
*
*       _StoreSelAP
*/
void _StoreSelAP(void) {
  JTAG_StoreIR(0xB);  // APACC command
  JTAG_StoreClocks(1);
}

/*********************************************************************
*
*       _StoreTriggerReadAPDPReg
*
*  Function description
*    Triggers a read of an AP or DP register. Depends on the previous command (DPACC / APACC)
*/
int _StoreTriggerReadAPDPReg(unsigned int RegIndex) {
  __int64 v;        // We need 35 bits: 32 data, 2 bit addr, 1 bit RnW
  int BitPosData;
  //
  // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
  //
  v = 0;
  v |= 1;                // 1 indicates read access
  v |= (RegIndex << 1);
  BitPosData = JTAG_StoreDR(v, 35);
  JTAG_StoreClocks(8);
  return BitPosData;
}

/*********************************************************************
*
*       _StoreWriteAPDPReg
*
*  Function description
*    Writes an AP or DP register. Depends on the previous command (DPACC / APACC)
*/
int _StoreWriteAPDPReg(unsigned int RegIndex, __int64 Data) {
  __int64 v;        // We need 35 bits: 32 data, 2 bit addr, 1 bit RnW
  int BitPosData;
  //
  // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
  //
  v = 0;   // 0 indicates write access
  v |= (RegIndex << 1);
  v |= (Data << 3);
  BitPosData = JTAG_StoreDR(v, 35);
  JTAG_StoreClocks(8);
  return BitPosData;
}

/********************************************************************* * * InitTarget * * Function description * Prepare LPC4350 for multi-core debugging * On the LPC4350 after reset there is only a Cortex-M4 present, * but it is possible to configure the device to also have a Cortex-M0 in the JTAG chain. * This is what this script does. */
void InitTarget(void) {
  int v;
  int BitPos;
  int Speed;
  int ResetStatRegAddr;
  int ResetCtrlregAddr;
  int ResetBitPosition;  

  Report("NXP LPC4350 (Cortex-M4+M0 core) J-Link script");
  Speed = JTAG_Speed;
  JTAG_Speed = 100;
  JTAG_Reset();                           // Perform TAP reset and J-Link JTAG auto-detection
  //
  // This script is able to handle all three versions of the LPC4350 silicon
  // 1st silicon: After power-up only the Cortex-M4 is in the JTAG chain, the Cortex-M0 needs to be added
  // 2nd silicon: After power-up the Cortex-M4 and the Cortex-M0 are in the JTAG chain. The Cortex-M4 is shown twice (bug, will be fixed in 3rd silicon)
  // 3rd silicon: After power-up the Cortex-M4 and the Cortex-M0 are in the JTAG chain.
  //
  if ((JTAG_TotalIRLen != 4) && (JTAG_TotalIRLen != 8) && (JTAG_TotalIRLen != 12)) {
    MessageBox("This script is designed for working with only a LPC4350 in the JTAG chain.");
    return 0;
  }
  //
  // If only the Cortex-M4 is in the chain, make sure that the Cortex-M0 is added
  //
  if (JTAG_TotalIRLen == 4) {
    JTAG_DRPre  = 0;
    JTAG_DRPost = 0;
    JTAG_IRPre  = 0;
    JTAG_IRPost = 0;
    JTAG_IRLen  = 4;
    Report("J-Link script: Enabling Cortex-M0.");
    _StoreSelDP();
    _StoreWriteAPDPReg(1, 0x50000020);          // Power up debug port and system port
    do {
      BitPos = _StoreTriggerReadAPDPReg(1);
      v = JTAG_GetU32(BitPos + 3);
    } while((v & 0xF0000000) != 0xF0000000);    // Wait until debug port and system port have been powered-up
    _StoreWriteAPDPReg(2, 0x00000000);          // Select AHB-AP
    _StoreSelAP();
    _StoreWriteAPDPReg(0, 0x23000012);          // AHB-AP CSW: 32-bit accesses, Address increment enabled
    //
    // Enable the Cortex-M4 and Cortex-M0 in the JTAG chain
    //
    _StoreWriteAPDPReg(1, 0x40043118);          // AHB-AP TAR
    _StoreWriteAPDPReg(3, 0x00000060);          // AHB-AP DRW
    JTAG_WriteClocks(1);
    _StoreSelDP();
    JTAG_WriteClocks(1);                        // Make sure all JTAG buffers are empty
    JTAG_Reset();
    if (JTAG_TotalIRLen != 8) {
      MessageBox("Error: Could not enable Cortex-M0.");
      JTAG_Speed = Speed;
      return 0;
    }
  }
  //
  // Handle cases:
  // 1st silicon: Cortex-M0 has been enabled
  // 3rd silicon: Cortex-M0 is already enabled after power-up
  //
  if (JTAG_TotalIRLen == 8) {
    //
    // Re-configure JTAG settings since we have 2 devices (Cortex-M4 and Cortex-M0 in the JTAG chain now)
    // #0: Cortex-M4
    // #1: Cortex-M0
    // We want to talk to the Cortex-M4
    //
    Report("J-Link script: Cortex-M0 already enabled.");
    JTAG_DRPre  = 0;
    JTAG_DRPost = 1;
    JTAG_IRPre  = 0;
    JTAG_IRPost = 4;
    JTAG_IRLen  = 4;
    CPU=CORTEX_M4;
    JTAG_SetDeviceId(0, 0x4BA00477);  // Device #0 is the Cortex-M4
    JTAG_SetDeviceId(1, 0x0BA01477);  // Device #1 is the Cortex-M0
  }
  //
  // Handle 2nd (buggy) silicon, which shows 3 devices in the JTAG chain
  // #0: Cortex-M4
  // #1: Cortex-M4  (not really present, bug in silicon)
  // #2: Cortex-M0
  // We want to talk to the Cortex-M4
  //
  if (JTAG_TotalIRLen == 12) {
    Report("J-Link script: Cortex-M0 already enabled.");
    JTAG_DRPre  = 0;
    JTAG_DRPost = 2;
    JTAG_IRPre  = 0;
    JTAG_IRPost = 8;
    JTAG_IRLen  = 4;
    CPU=CORTEX_M4;
    JTAG_SetDeviceId(0, 0x4BA00477);  // Device #0 is the Cortex-M4
    JTAG_SetDeviceId(1, 0x0BA01477);  // Device #1 is the Cortex-M4 with wrong ID. Only present on buggy silicon
    JTAG_SetDeviceId(2, 0x0BA01477);  // Device #1 is the Cortex-M0
  }
  JTAG_WriteClocks(1);
  JTAG_Speed = Speed;
}

LPC4350_DebugCortexM0.JLinkScript

/*********************************************************************
*               SEGGER MICROCONTROLLER GmbH & Co KG                  *
*       Solutions for real time microcontroller applications         *
**********************************************************************
*                                                                    *
*       (c) 2011  SEGGER Microcontroller GmbH & Co KG                *
*                                                                    *
*       www.segger.com     Support: support@segger.com               *
*                                                                    *
**********************************************************************
----------------------------------------------------------------------
Purpose : J-Link script file for NXP LPC4350 device.
          The NXP LPC4350 is a Cortex-M4 based device which has an
          additional Cortex-M0 core inside which can be enabled.
          This script is used to configure the J-Link to talk to the Cortex-M0 core.
 This script assumes that LPC4350_DebugCortexM4.JLinkScript has already been executed before using this script file.
---------------------------END-OF-HEADER------------------------------
*/

/*********************************************************************
*
*       ResetTarget
*
*  Function description
*    Do nothing. We can not reset the Cortex-M0 while debugging on it since
*    It does not come out of reset automatically. So once if has been reset
*    Only the M4 is able to get it out of the reset state.
*/
void ResetTarget(void) {
  int Speed;

  Report("J-Link script: Performing reset sequence");
  Speed = JTAG_Speed;
  JTAG_Speed = 100;
  JTAG_WriteClocks(1);
  JTAG_Speed = Speed;
}

/*********************************************************************
*
*       InitTarget
*
*  Function description
*    Select the Cortex-M0 as the device we want to debug
*    If it is not already enabled we are done here, because configuration
*    has to be done when setting up the Cortex-M4 debug session
*/
void InitTarget(void) {
  int v;
  int BitPos;
  int Speed;
  //
  // This script is able to handle all three versions of the LPC4350 silicon
  // 1st silicon: After power-up only the Cortex-M4 is in the JTAG chain, the Cortex-M0 needs to be added
  // 2nd silicon: After power-up the Cortex-M4 and the Cortex-M0 are in the JTAG chain. The Cortex-M4 is shown twice (bug, will be fixed in 3rd silicon)
  // 3rd silicon: After power-up the Cortex-M4 and the Cortex-M0 are in the JTAG chain.
  //
  Report("NXP LPC4350 (Cortex-M4+M0 core) J-Link script");
  Speed = JTAG_Speed;
  JTAG_Speed = 100;
  JTAG_Reset();                           // Perform TAP reset and J-Link JTAG auto-detection
  //
  // Check if the Cortex-M0 is already enabled
  // If not, we are done here
  //
  if ((JTAG_TotalIRLen != 8) && (JTAG_TotalIRLen != 12)) {
    MessageBox("LPC4350_DebugCortexM4.JLinkScript has to be executed prior to this script.");
    JTAG_Speed = Speed;
    return 0;
  }
  //
  // Configure the JTAG chain to talk to the LPC4350 Cortex-M0 core
  //
  if (JTAG_TotalIRLen == 8) {
    JTAG_DRPre  = 1;
    JTAG_DRPost = 0;
    JTAG_IRPre  = 4;
    JTAG_IRPost = 0;
    JTAG_IRLen  = 4;
    JTAG_SetDeviceId(0, 0x4BA00477);  // Device #0 is the Cortex-M4
    JTAG_SetDeviceId(1, 0x0BA01477);  // Device #1 is the Cortex-M0
  } else {
    JTAG_DRPre  = 2;
    JTAG_DRPost = 0;
    JTAG_IRPre  = 8;
    JTAG_IRPost = 0;
    JTAG_IRLen  = 4;
    JTAG_SetDeviceId(0, 0x4BA00477);  // Device #0 is the Cortex-M4
    JTAG_SetDeviceId(1, 0x0BA01477);  // Device #1 is the Cortex-M4 (only visible on buggy silicon)
    JTAG_SetDeviceId(2, 0x0BA01477);  // Device #1 is the Cortex-M0
  }
  CPU=CORTEX_M0;
  JTAG_Speed = Speed;
}

CREG5 control register

Use this register to disable the JTAG for the M4 main core and the M0 co-processors.

By default the JTAG access is enabled unless an AES key is programmed and the device is a secure device.

Remark: Disabling the JTAG can only be reversed by resetting the part through any available reset.

Table 99. CREG5 control register (CREG5, address 0x4004 3118) bit description

10 M0SUBTAPSEL JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.

11 M4TAPSEL JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.

12 M0APPTAPSEL JTAG debug disable for M0APP co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.

--------------------------------------------------------------------------------
// Power Up First J-Link Commander
--------------------------------------------------------------------------------
Info: TotalIRLen = 12, IRPrint = 0x0111
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 3 JTAG devices, Total IRLen = 12: #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM) #1 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM) #2 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
J-Link>mem 40043118 4
40043118 = 70 02 00 40 J-Link>w4 40043118 40000670
Writing 40000670 -> 40043118
J-Link>mem 40043118 4
40043118 = 03 00 00 00
J-Link>
--------------------------------------------------------------------------------
// Second J-Link Commander after w4 40043118 40000670
--------------------------------------------------------------------------------
Info: TotalIRLen = 8, IRPrint = 0x0011
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 2 JTAG devices, Total IRLen = 8: #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM) #1 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
J-Link>mem 40043118 4
40043118 = 70 06 00 40 J-Link>w4 40043118 40001670
Writing 40001670 -> 40043118
J-Link>mem 40043118 4
40043118 = 01 00 00 00
J-Link>
--------------------------------------------------------------------------------
// Third J-Link Commander after w4 40043118 40001670
--------------------------------------------------------------------------------
Info: TotalIRLen = 4, IRPrint = 0x01
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 1 JTAG device, Total IRLen = 4: #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
J-Link>mem 40043118 4
40043118 = 70 16 00 40 J-Link>w4 40043118 40001E70
Writing 40001E70 -> 40043118
J-Link>
--------------------------------------------------------------------------------
// Fourth J-Link Commander after w4 40043118 40001E70
--------------------------------------------------------------------------------
No device found at all. Selecting JTAG as default target interface.
J-Link>r0 J-Link>r1 J-Link>
--------------------------------------------------------------------------------
// All JTAG TAPs are endabled again
--------------------------------------------------------------------------------
Info: TotalIRLen = 12, IRPrint = 0x0111
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 3 JTAG devices, Total IRLen = 12: #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM) #1 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM) #2 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz

//------------------------------------------------------------------------------
// Power Up First J-Link Commander
//------------------------------------------------------------------------------
Info: TotalIRLen = 12, IRPrint = 0x0111 <--- Device #2 : Device #1 : Device #0
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 3 JTAG devices, Total IRLen = 12:
 #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
 #1 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
 #2 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
J-Link>mem 40043118 4
40043118 = 70 02 00 40
J-Link>w4 40043118 40000670
Writing 40000670 -> 40043118
J-Link>mem 40043118 4
40043118 = 03 00 00 00
J-Link>
//------------------------------------------------------------------------------
// Second J-Link Commander after w4 40043118 40000670
//------------------------------------------------------------------------------
Info: TotalIRLen = 8, IRPrint = 0x0011 <--- Device #1 : Device #0
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 2 JTAG devices, Total IRLen = 8:
 #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
 #1 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
J-Link>mem 40043118 4
40043118 = 70 06 00 40
J-Link>w4 40043118 40001670
Writing 40001670 -> 40043118
J-Link>mem 40043118 4
40043118 = 01 00 00 00
J-Link>
//------------------------------------------------------------------------------
// Third J-Link Commander after w4 40043118 40001670
//------------------------------------------------------------------------------
Info: TotalIRLen = 4, IRPrint = 0x01 <--- Device #0
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 1 JTAG device, Total IRLen = 4:
 #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
J-Link>mem 40043118 4
40043118 = 70 16 00 40
J-Link>w4 40043118 40001E70
Writing 40001E70 -> 40043118
J-Link>
//------------------------------------------------------------------------------
// Fourth J-Link Commander after w4 40043118 40001E70
//------------------------------------------------------------------------------
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
No devices found on JTAG chain. Trying to find device on SWD.
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
No device found on SWD.
Trying to find device on FINE interface.
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
No device found on FINE interface.
Did not find any core.
Failed to identify target. Trying again with slow (4 kHz) speed.
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
No devices found on JTAG chain. Trying to find device on SWD.
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
No device found on SWD.
Trying to find device on FINE interface.
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
Info: TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
No device found on FINE interface.
Did not find any core.
No device found at all. Selecting JTAG as default target interface.
J-Link>
J-Link>r0
J-Link>r1
J-Link>
//------------------------------------------------------------------------------
// All JTAG TAPs are endabled again
//------------------------------------------------------------------------------
Info: TotalIRLen = 12, IRPrint = 0x0111 <--- Device #2 : Device #1 : Device #0
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 3 JTAG devices, Total IRLen = 12:
 #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
 #1 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
 #2 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
//------------------------------------------------------------------------------
// Try to enable again but failed : 40001270 can not be changed to 40000270
//------------------------------------------------------------------------------
J-Link>w4 40043118 40000270
Writing 40000270 -> 40043118
J-Link>mem 40043118 4
40043118 = 70 12 00 40
J-Link>
//------------------------------------------------------------------------------
Info: TotalIRLen = 8, IRPrint = 0x0011 <--- Device #1 : Device #0
Info: Found Cortex-M4 r0p1, Little endian.
Info: FPUnit: 6 code (BP) slots and 2 literal slots
Info: CoreSight components:
Info: ROMTbl 0 @ E00FF000
Info: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
Info: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
Info: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
Info: ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
Info: ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
Info: ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Found 2 JTAG devices, Total IRLen = 8:
 #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
 #1 Id: 0x0BA01477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
Cortex-M4 identified.
Target interface speed: 100 kHz
J-Link>mem 40043118 4
40043118 = 70 12 00 40
//------------------------------------------------------------------------------

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