實測—fft IP核使用（包括ifft的配置使用）

時間 2019-12-06

標籤實測 fft 使用包括 ifft 配置简体版

原文原文鏈接

Vivado xilinx fft9.0 使用筆記：spa

****注仿真實測1024點的轉換須要通過1148個時鐘週期才能獲得轉換結果；3d

模塊配置信號含義請參考pg109文檔手冊（寫的賊爛會看暈），不詳細說明；blog

1、查找fft IP核按以下幾圖配置可實現正確的fft轉換結果：ip

配置1個轉換通道；轉換數據長度是1024 points；選擇流線型結構類型pipelined,streamingI/O，優勢並行轉換速度快，,缺點佔用資源多。如圖1：ci

圖1資源

如圖2，設置數據類型爲定點小數；縮減因子設置成Unscaled；RoundingModes設置成Truncation；輸入位寬設置24位，精度設置16；Output Ordering 設置成Natural Order；OptionalOutputFieldds勾選XK_INDEX；文檔

圖2get

如圖3 此頁信息基本固定配置：input

圖3it

***注：注意圖4中區域有助於幫助你在編寫testbenchs時對s_axis_config_tdata進行配置；

如圖4 s_axis_config_tdata 只有1位配置fft的fwd/inv;

圖4

Testbench代碼以下：

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer: zyp

// Create Date: 04/21/2017 08:35:42 PM

// Design Name:

// Module Name: test

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module test();

// Inputs

reg aclk;

reg aresetn;//active low

reg s_axis_config_tvalid;

reg s_axis_data_tvalid;

reg s_axis_data_tlast;

reg m_axis_data_tready;

reg [7:0] s_axis_config_tdata;

//reg [15:0] s_axis_config_tdata;

reg [47: 0] s_axis_data_tdata;

// Outputs

wire s_axis_config_tready;

wire s_axis_data_tready;

wire m_axis_data_tvalid;

wire m_axis_data_tlast;

wire event_frame_started;

wire event_tlast_unexpected;

wire event_tlast_missing;

wire event_status_channel_halt;

wire event_data_in_channel_halt;

wire event_data_out_channel_halt;

//wire [47:0] m_axis_data_tdata;

wire [79:0] m_axis_data_tdata; //un_scaled

wire [15:0] m_axis_data_tuser;

//reg[23:0] XK_RE;

//reg[23:0] XK_IM;

reg[39:0] XK_RE;//config unsclaed

reg[39:0] XK_IM;//config unsclaed

reg[23:0] mem0_re[0:4095];

reg[23:0] mem1_re[0:7];

reg[23:0] mem2_re[0:7];

initial $readmemh("D:/fpga/fft1/stimulus0_24bit.dat",mem0_re);

initial $readmemh("D:/fpga/fft1/stimulus1_24bit.dat",mem1_re);

initial $readmemh("D:/fpga/fft1/stimulus2_24bit.dat",mem2_re);

reg[7:0] op_sample= 0;

reg op_sample_first = 1;

reg[7:0] ip_frame=0;

reg[7:0] op_frame=0;

integer i;

// generate clk

always #5 aclk =! aclk;

xfft_0 xfft_m0 (

.aclk(aclk), // input wire aclk

// .aresetn(aresetn),

.s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata

.s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid

.s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready

.s_axis_data_tdata(s_axis_data_tdata), // input wire [47 : 0] s_axis_data_tdata

.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid

.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready

.s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast

.m_axis_data_tdata(m_axis_data_tdata), // output wire [47 : 0] m_axis_data_tdata

.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid

.m_axis_data_tready(m_axis_data_tready), // input wire m_axis_data_tready

.m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast

.m_axis_data_tuser(m_axis_data_tuser),//XK_INDEX

.event_frame_started(event_frame_started), // output wire event_frame_started

.event_tlast_unexpected(event_tlast_unexpected), // output wire event_tlast_unexpected

.event_tlast_missing(event_tlast_missing), // output wire event_tlast_missing

.event_status_channel_halt(event_status_channel_halt), // output wire event_status_channel_halt

.event_data_in_channel_halt(event_data_in_channel_halt), // output wire event_data_in_channel_halt

.event_data_out_channel_halt(event_data_out_channel_halt) // output wire event_data_out_channel_halt

);

initial begin

// Initialize Inputs

aclk = 0;

aresetn = 0;

s_axis_config_tvalid = 0;

s_axis_config_tdata = 0;

s_axis_data_tvalid = 0;

s_axis_data_tdata = 0;

s_axis_data_tlast = 0;

m_axis_data_tready = 0;

// Wait 150 ns for global reset to finish

#150;

aresetn = 1;

m_axis_data_tready = 1;

s_axis_config_tvalid = 1;

//s_axis_config_tdata = 16'b10110101011; // 512points bit0-9 sclae_sch bit10 fwd/ivs 這樣配置不對 FFT desired (and not IFFT

//s_axis_config_tdata = 16'b01101010111; // 512points bit1-10 sclae_sch bit0 fwd/ivs 按這組數據配置結果縮小了1000倍 FFT desired (and not IFFT

//s_axis_config_tdata = 16'b00000000001; // 512points result 與下一種狀況一致

s_axis_config_tdata = 1'b1; // 配置fwd 512 or 1024 points 配置unscale 狀況位寬有進位輸出位寬要對應結果正確正確！！！！！

//s_axis_config_tdata = 16'b1101101010111;//4096points bit1-12 sclae_sch bit0 fwd/ivs

//s_axis_data_tlast = 1;

s_axis_data_tdata = 48'h000000;

s_axis_data_tvalid = 0;

#10

s_axis_config_tvalid = 0;

begin

for(i=0;i<1024;i=i+1) begin

#10

s_axis_data_tvalid <= 1;

s_axis_data_tdata <= {{24'h000000},mem0_re[i]};

$display("mem_a[%d] = %h", i, mem0_re[i]);

end

assign XK_RE = m_axis_data_tdata[39:0];

assign XK_IM = m_axis_data_tdata[79:40];

#10;

s_axis_data_tdata = 48'h000000;

s_axis_data_tvalid = 0;

#400000 $finish;

end

endmodule

/*test smaple 1 N=8 (?????s_axis_config_tdata = 8'b00000001);

s_axis_data_tdata =[1.1 2.1 3.1 4.1 5.1 6.1 7.1 8.1] 16位定點小數

s_axis_data_tdata =[1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a] 16位定點小數

vivado_result 00000024ccd0 09a820fc0000 040000fc0000 01a820fc0000 000000fc0000 fe57e0fc0000 fc0000fc0000 f657e0fc0000

matlab_result 36.8000+0.0000i -4.0000+9.6569i -4.0000+4.0000i -4.0000+1.6569i -4.0000+0.0000i -4.0000-1.6569i -4.0000-4.0000i -4.0000-9.6569i

s_axis_config_tdata = 8'b00000000或者不配置

vivado_result 00000024ccd0 f657e0fc0000 fc0000fc0000 fe57e0fc0000 000000fc0000 01a820fc0000 040000fc0000 09a820fc0000

compare result right!!!!!

/*test sample 2 N=16 (?????s_axis_config_tdata = 8'b00000001);

s_axis_data_tdata =[1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a] 16點 16位定點小數

vivado_result 0000004999a0 000000000000 135040f80000 000000000000 080000f80000 000000000000 035040f80000 000000000000 000000f80000 000000000000 fcafc0f80000 000000000000 f80000f80000 000000000000 ecafc0f80000 000000000000

matlab_result 73.6000+0.0000i 0.0000+0.0000i -8.0000+19.3137i 0.0000+0.0000i -8.0000+8.0000i 0.0000+0.0000i -8.0000+3.3137i 0.0000+0.0000i -8.0000+0.0000i 0.0000+0.0000i -8.0000-3.3137i 0.0000+0.0000i -8.0000-8.0000i 0.0000+0.0000i -8.0000-19.3137i 0.0000+0.0000i

compare result right!!!!!

/*test sample 3 N=128 (s_axis_config_tdata = 16'b0000000000000001;error )

s_axis_config_tdata = 16'b0101010101010101;error

s_axis_data_tdata =[1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a]*8 16位定點小數

*****注：其中輸入數據"D:/fpga/fft1/stimulus0_24bit.dat"爲16位定點小數以下：

1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a

Vivado simulation result 如圖所示：

圖5

將上述輸入數據轉換成16爲定點小數爲a=[1.1 2.1 3.1 4.1 5.1 6.1 7.1 8.1……..] b=fft(a) MATLAB仿真結果如圖：

圖6

對比圖5、圖6可知結果保持一致。

2、配置IP覈實現ifft轉換

Testbench 代碼以下：

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer: zyp

// Create Date: 04/21/2017 08:35:42 PM

// Design Name:

// Module Name: test

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

// 對512點作ifft變換

// 512樣本數據來自【1.1 2.1 3.1 4.1 5.1 6.1 7.1 8.1......】的fft轉換結果

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module testbench_ifft();

//ifft_0信號

// Inputs

reg aclk;

reg aresetn;//active low

reg rst;

reg s_axis_config_tvalid;

reg s_axis_data_tvalid;

reg s_axis_data_tlast;

reg m_axis_data_tready;

reg [7:0] s_axis_config_tdata;

reg [63: 0] s_axis_data_tdata;

// Outputs

wire s_axis_config_tready;

wire s_axis_data_tready;

wire m_axis_data_tvalid;

wire m_axis_data_tlast;

wire event_frame_started;

wire event_tlast_unexpected;

wire event_tlast_missing;

wire event_status_channel_halt;

wire event_data_in_channel_halt;

wire event_data_out_channel_halt;

wire [95:0] m_axis_data_tdata; //un_scaled

wire [15:0] m_axis_data_tuser;

reg[47:0] XK_RE;//ceshi xianshi

reg[47:0] XK_IM;//ceshi xianshi

reg[23:0] mem0_re[0:4095];

reg[63:0] mem3_re[0:511];//高40位是虛部 34位爲有效低40位是實部 34位有效 16位定點小數

reg[23:0] mem1_re[0:7];

reg[23:0] mem2_re[0:7];

initial $readmemh("D:/fpga/fft1/stimulus0_24bit.dat",mem0_re);

initial $readmemh("D:/fpga/fft1/stimulus1_24bit.dat",mem1_re);

initial $readmemh("D:/fpga/fft1/stimulus2_24bit.dat",mem2_re);

initial $readmemh("D:/fpga/fft1/stimulus3_80bit.dat",mem3_re);

reg[7:0] op_sample= 0;

reg op_sample_first = 1;

reg[7:0] ip_frame=0;

reg[7:0] op_frame=0;

integer i;

reg[11:0] cnt;

// generate clk

always #5 aclk =! aclk;

ifft_0 ifft_m0 (