1.從原理圖導出管腳分配文件，這個適用於altera xilinx的管腳分配blog
2.對於DDR的管腳分配，咱們能夠在MIG IP配置時，直接在IP核配置中輸入管腳分配；get
在這個界面中，若是事先有準備好的XDC/UCF文件，可用read xdc/ucf導入DDR3的管腳分配文件；同時也能夠save pinout把管腳分配保存到新的xdc/ucf文件中；class
3.其餘的管腳咱們能夠在xdc文件中手動輸入對應管腳，對應管腳的電平；原理
set_property IOSTANDARD LVCMOS15 [get_ports led]
set_property PACKAGE_PIN Y10 [get_ports led]配置
4.對BUS，對信號線必定要加上{}；im
set_property PACKAGE_PIN A16 [get_ports {adv7393_data[15]}]
set_property PACKAGE_PIN C16 [get_ports {adv7393_data[14]}]
set_property PACKAGE_PIN B17 [get_ports {adv7393_data[13]}]
set_property PACKAGE_PIN A17 [get_ports {adv7393_data[12]}]
set_property PACKAGE_PIN H20 [get_ports {adv7393_data[11]}]
set_property PACKAGE_PIN D16 [get_ports {adv7393_data[10]}]
set_property PACKAGE_PIN F17 [get_ports {adv7393_data[9]}]
set_property PACKAGE_PIN H19 [get_ports {adv7393_data[8]}]
set_property PACKAGE_PIN G17 [get_ports {adv7393_data[7]}]
set_property PACKAGE_PIN G18 [get_ports {adv7393_data[6]}]
set_property PACKAGE_PIN K20 [get_ports {adv7393_data[5]}]
set_property PACKAGE_PIN J19 [get_ports {adv7393_data[4]}]
set_property PACKAGE_PIN L18 [get_ports {adv7393_data[3]}]
set_property PACKAGE_PIN K18 [get_ports {adv7393_data[2]}]
set_property PACKAGE_PIN J17 [get_ports {adv7393_data[1]}]
set_property PACKAGE_PIN K19 [get_ports {adv7393_data[0]}]img