arm 指令架構

the arm instruction set

 

the arm has six operation modes:

 

user (unprivileged mode under which most tasks run)

fiq (entered when a hight priority(fast) interrrupt is raised)

irq (entered whene a low priority(normal ) interrrupt is raised )

supervisor( entered on reset and when a software interrupt instruction is executed )

swi 指令

abort( used to handle memory access violations) 用於處理 memory access violations

undef( used to handle undefined instructions)

system (privileged mode using the same registers as user mode )

 

37個寄存器

1 pc

1 cpsr

5 spsr

30 通用寄存器

 

特權模式纔有

spsr

 

r13 = sp

r14 = lr

 

user mode return address calculated from user mode pc value

and stored in fiq mode lr

 

user mode cpsr copied to fiq mode spsr

 CPSR有4個8位區域 標誌域（F-flag）、狀態域（S-status）、擴展域（X-extention）、控制域（C-control）

C 控制域屏蔽字節(psr[7:0])
      X 擴展域屏蔽字節(psr[15:8])
      S 狀態域屏蔽字節(psr[23:16])
      F 標誌域屏蔽字節(psr[31:24])

如: msr    CPSR_fc,  r0

n negative

z zero

c carried out

v verflowed

all instruction are 32 bits in length 32長度的指令

all instructions must be word aligned 字對齊

pc 值存儲 31：2

1:0 equal to zero

r14 is used as the subroutine link register(LR) and stored the return address

whene branch with link operations are performed,

 

mov r15, r14

mov pc, lr : lr--->pc

 

0x0 reset

0x04 undefined instruction

0x08 software interrupt

0x0c prefetch abort

0x10 data abort

0x14 reservered

0x18 irq

0x1c fiq

 

異常的過程

copy cpsr to spsr_<mode>

set appropriate cpsr

maps in appropriate banked registers

stores the "return address" in lr_<mode>

sets pc to vector address

 

restore cpsr from spsr_<mode>

restore pc from lr_<mode>

 

the instruction pipeline

 

the arm used a pipeline in order to increase the speed of the flow of instruction to the processor

 

 

pc 　　fetch　　instruction fetched from memory

pc-4  decode　　decoding of registers used in instruction

pc-8 execute register read from register bank shift and alu operation

 

pc rahter than pointing to the instruction being executed (不是指向要執行的) but points to the instruction being fetched

 而是要取的指令