vivado 建立PL工程

時間 2019-11-30

標籤 vivado 建立工程简体版

原文原文鏈接

參考來源

https://china.xilinx.com/video/hardware/i-and-o-planning-overview.htmlhtml

前言

我Win10系統上的Xilinx Platform Studio打不開，無奈之下換用Vivado。這篇粗略地介紹Vivado建立FPGA工程的流程ide

使用Vivado

新建工程

打開vivado，點New Project而後Create a New Vivado Project點next再填寫工程名、工程路徑點next
在Project Type選擇 RTL 工程，單擊 NEXT工具

選擇板子，個人是Zedboard，而後next-finish
開發工具

設計輸入

界面以下，圖片來源https://blog.csdn.net/kenjianqi1647/article/details/79199657
優化

代碼

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Flowing LED
-- 先分頻再移位
entity LED is
    port(
    GCLK,BTNU:in std_logic;
    LDS:out std_logic_vector(7 downto 0)
    );
end LED;


architecture Behavioral of LED is
-- 計數
signal count:std_logic_vector(25 downto 0);
signal clk_temp:std_logic;
signal LDS_temp:std_logic_vector(7 downto 0):="00000001";
begin

    process(GCLK,BTNU)  
    --分頻係數
    variable N :std_logic_vector(25 downto 0):="10111110101111000010000000";
    begin  
        if BTNU='1' then
            count<="00000000000000000000000001"; 
            clk_temp<='1';  
            
        elsif (GCLK'EVENT and GCLK='1')then 
            if (count=N)then
                count<="00000000000000000000000001";
                clk_temp<='1';
            else
                count<=count+1;
                clk_temp<='0';
            end if;
        end if;
    end process;
    --獲得的clk_temp爲2Hz，佔空比1/50000000
    
    process(clk_temp,BTNU)
    begin
        if BTNU='1' then
            LDS_temp<="00000001";
        elsif (clk_temp'EVENT and clk_temp='1')then
            LDS_temp(0)<=LDS_temp(7);
            LDS_temp(7 downto 1)<=LDS_temp(6 downto 0);
        end if;
    end process;
    LDS<=LDS_temp;
end Behavioral;

引腳約束

NET "BTNU" IOSTANDARD = LVCMOS18;
NET "GCLK" IOSTANDARD = LVCMOS33;


NET "BTNU" LOC = T18;
NET "GCLK" LOC = Y9;
NET "LDS[7]" LOC = U14;
NET "LDS[6]" LOC = U19;
NET "LDS[5]" LOC = W22;
NET "LDS[4]" LOC = V22;
NET "LDS[3]" LOC = U21;
NET "LDS[2]" LOC = U22;
NET "LDS[0]" LOC = T22;
NET "LDS[1]" LOC = T21;

# PlanAhead Generated IO constraints 

NET "LDS[7]" IOSTANDARD = LVCMOS33;
NET "LDS[6]" IOSTANDARD = LVCMOS33;
NET "LDS[5]" IOSTANDARD = LVCMOS33;
NET "LDS[4]" IOSTANDARD = LVCMOS33;
NET "LDS[3]" IOSTANDARD = LVCMOS33;
NET "LDS[2]" IOSTANDARD = LVCMOS33;
NET "LDS[1]" IOSTANDARD = LVCMOS33;
NET "LDS[0]" IOSTANDARD = LVCMOS33;

設計綜合

設計綜合過程會完成語法檢查，編譯，映射等步驟
點擊Run Synthesis，能夠在Project Summary 查看狀態

綜合完畢後
點擊open synthesized design打開synthesized design，此時點擊菜單欄的window-I/O ports 便可規劃管腳。點擊菜單欄Layout-I/O planning打開Package
.net

設計實現

點擊Run Implementation，完成後點擊Generate Bitstream，生成比特文件設計

下載執行

將開發板通電並鏈接到電腦，點擊Hardware Manager ，在fpga芯片上右鍵program，
3d

現象

8個LED從右到左流水點亮，若是按BTNU從LED0開始從新流水點亮調試

使用ISE

流程：建立工程、設計輸入、引腳約束、設計綜合、設計實現、生成比特文件、下載執行code

開發工具

ISE

硬件鏈接

Zedboard 的8個LED共陰極，置高電平點亮
100MHz時鐘源接入GCLK引腳
BTNU按鈕按下時是高電平，可用於高電平復位

器件屬性配置

代碼

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Flowing LED
-- 先分頻再移位
entity LED is
    port(
    GCLK,BTNU:in std_logic;
    LDS:out std_logic_vector(7 downto 0)
    );
end LED;


architecture Behavioral of LED is
-- 計數
signal count:std_logic_vector(25 downto 0);
signal clk_temp:std_logic;
signal LDS_temp:std_logic_vector(7 downto 0):="00000001";
begin

    process(GCLK,BTNU)  
    --分頻係數
    variable N :std_logic_vector(25 downto 0):="10111110101111000010000000";
    begin  
        if BTNU='1' then
            count<="00000000000000000000000001"; 
            clk_temp<='1';  
            
        elsif (GCLK'EVENT and GCLK='1')then 
            if (count=N)then
                count<="00000000000000000000000001";
                clk_temp<='1';
            else
                count<=count+1;
                clk_temp<='0';
            end if;
        end if;
    end process;
    --獲得的clk_temp爲2Hz，佔空比1/50000000
    
    process(clk_temp,BTNU)
    begin
        if BTNU='1' then
            LDS_temp<="00000001";
        elsif (clk_temp'EVENT and clk_temp='1')then
            LDS_temp(0)<=LDS_temp(7);
            LDS_temp(7 downto 1)<=LDS_temp(6 downto 0);
        end if;
    end process;
    LDS<=LDS_temp;
end Behavioral;

引腳約束

NET "BTNU" IOSTANDARD = LVCMOS18;
NET "GCLK" IOSTANDARD = LVCMOS33;


NET "BTNU" LOC = T18;
NET "GCLK" LOC = Y9;
NET "LDS[7]" LOC = U14;
NET "LDS[6]" LOC = U19;
NET "LDS[5]" LOC = W22;
NET "LDS[4]" LOC = V22;
NET "LDS[3]" LOC = U21;
NET "LDS[2]" LOC = U22;
NET "LDS[0]" LOC = T22;
NET "LDS[1]" LOC = T21;

# PlanAhead Generated IO constraints 

NET "LDS[7]" IOSTANDARD = LVCMOS33;
NET "LDS[6]" IOSTANDARD = LVCMOS33;
NET "LDS[5]" IOSTANDARD = LVCMOS33;
NET "LDS[4]" IOSTANDARD = LVCMOS33;
NET "LDS[3]" IOSTANDARD = LVCMOS33;
NET "LDS[2]" IOSTANDARD = LVCMOS33;
NET "LDS[1]" IOSTANDARD = LVCMOS33;
NET "LDS[0]" IOSTANDARD = LVCMOS33;

現象

8個LED從右到左流水點亮，若是按BTNU從LED0開始從新流水點亮

關於邏輯部分

通用FPGA邏輯部分以下所示

zynq的PL部分的特殊資源包括知足密集存儲的塊RAM和用於高速算術的DSP48E1。固然邏輯資源也能夠用來搭建RAM，可是塊RAM是通過優化的，使用很小的物理空間就能夠存儲大量數據；邏輯資源的查找表(LUT)也能夠用來算術運算，可是會佔用不少邏輯資源，DSP48E1是專用於長字長信號的高速算術運算的邏輯塊。