利用profiler工具提升NC-Verilog仿真效率

你們進行芯片驗證時，通常都會遇到仿真速度很慢、效率不高的問題。
目前發現了一個方法能夠debug上述問題。即，利用NC的profiler工具。

關於profiler工具，我把文檔《Cadence® NC-Verilog® Simulator Help》中的原文貼出來：
The profiler is a tool that measures where CPU time is spent during simulation. Although it was developed primarily to help Cadence R&D diagnose performance bottlenecks in the simulator, some of the information in the output file can help you to identify inefficient HDL coding practices. Once you have determined what code the simulator is spending most of its time running, improving the efficiency of this code will have the greatest effect on simulation performance.
The profiler works by interrupting the simulation at regular intervals (currently 100 times per second) and noting what was executing at that time. It keeps track of the number of 「hits」 on different activities, which approximates the amount of CPU time spent in these activities.
The profiler is easy to run and has minimal impact on simulation performance and memory usage. To run the profiler, use the -profile command-line option when you invoke the simulator (ncsim). Use +ncprofile if you are running in single-step invocation mode with the ncverilog command.

就是說，NC-Verilog在仿真引擎內集成了一個profiler工具，該工具每秒中斷仿真器100次，並在終端記錄下來，仿真結束時會生成一個日誌文件（ncprof.out）。
日誌文件裏會列出被中斷次數最多的模塊、代碼行和結構類型，這些信息能夠幫助診斷是哪些代碼或模塊在仿真時耗費了最多的時間。
經過修改這些模塊，就能提高仿真效率。而Profiler功能自己，對仿真只產生很是小的影響。

咱們經過-profile選項打開上述功能，仿真命令以下：

ncverilog +ncprofile <other_options> 

或者

ncsim –profile snapshot_name <other_options>