CRC校驗碼

例如:g(x)=x^4+x^3+x^2+1,(7,3)碼,信息碼110產生的CRC碼就是1001。
對於g(x)=x^4+x^3+x^2+1的解釋:(都是從右往左數)x4就是第五位是1,由於沒有x1因此第2位就是0。
11101 | 110,0000(設a=11101 ,b=1100000)
用b除以a作模2運算獲得餘數:1001
餘數是1001,因此CRC碼是1001,傳輸碼爲:110,1001
以原始數據長度爲496的CRC16的譯碼程序爲例,下面給出師兄的Verilog代碼:

module CRC16_cal(
  input clk,
  input rst,
  input data_in,
  input data_in_valid,
  output [15:0] CRC_out,
  output reg CRC_finish_flag
);
reg [511:0] data_reg;
reg [5:0] state;
reg [8:0] input_counter;
reg [8:0] shift_counter;
parameter state_input=6'b000001;
parameter state_calculate=6'b000010;
parameter gen_poly=17'b10000100000010001;html

assign CRC_out=data_reg[16:1];.net

always @(posedge clk or posedge rst)
if(rst==1'b1)
begin
  CRC_finish_flag<=1'b0;
  data_reg<=512'd0;
  state<=state_input;
  input_counter<=9'd0;
  shift_counter<=9'd0;
end
else
begin
  case(state)
    state_input:
    begin
      CRC_finish_flag<=1'b0;
      if(data_in_valid==1'b1)
      begin
        data_reg[495]<=data_in;
        data_reg[494:0]<=data_reg[495:1];
        if(input_counter==9'd495)
        begin
          state<=state_calculate;
          input_counter<=9'd0;
        end
        else
          input_counter<=input_counter+9'd1;
      end
    end
    state_calculate:
    begin
      if(data_reg[0]==1'b0)
      begin
        if(shift_counter==9'd495)
        begin
          CRC_finish_flag<=1'b1;
          state<=state_input;
          shift_counter<=9'd0;
        end
        else
        begin
          shift_counter<=shift_counter+9'd1;
          data_reg[510:0]<=data_reg[511:1];
          data_reg[511]<=1'b0;
        end
      end
      else
      begin
        data_reg[16:0]<=data_reg[16:0]^gen_poly;
      end
    end
    default state<=state_input;
  endcase
endhtm

endmoduleblog

 

//以上代碼的主體部分則爲state_calculate中的一段代碼,以下flux

if(data_reg[0]==1'b0)
begin
  data_reg[510:0]<=data_reg[511:1];
  data_reg[511]<=1'b0;
end
else
  data_reg[16:0]<=data_reg[16:0]^gen_poly;get

該段代碼循環執行shift_counter次,shift_counter = length(data_CRC) - length(gen_poly)  = = 512 - 17 = length(data_org) - 1 = 496 - 1  = 495.input

 
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