void RCC_DeInit(void)安全
{ui
/*Set HSION bit,內部高速時鐘使能HSI振盪器打開*/it
RCC->CR |=(uint32_t)0x00000001;io
/*Reset CFGR register,select
31:30--00:選擇系統時鐘 (SYSCLK) 輸出到 MCO2 引腳im
27:29--0xx:MCO2 預分頻器 (MCO2 prescaler)無分頻di
24:26--0xx:MCO1 預分頻器 (MCO1 prescaler)無分頻vi
23--0:PLLI2S 時鐘用做 I2S 時鐘源void
22:21--00:選擇 HSI 時鐘輸出到 MCO1 引腳ab
20:16--00000:無時鐘,適用於 RTC 時鐘的 HSE 分頻係數
15:13--0xx:AHB 時鐘不分頻
12:10--0xx:AHB 時鐘不分頻
9:8 保留,必須保持復位值
7:4--AHB 預分頻器 (AHB prescaler),0xxx:系統時鐘不分頻
3:2 --SWS:系統時鐘切換狀態 (System clock switch status),00:HSI 振盪器用做系統時鐘
1:0-- SW:系統時鐘切換 (System clock switch),00:選擇 HSI 振盪器做爲系統時鐘*/
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits
HSEON:0:HSE 振盪器關閉,HSE 時鐘使能 (HSE clock enable)
CSSON:時鐘安全系統使能 (Clock security system enable),0:時鐘安全系統關閉(時鐘監測器關閉)
PLLON:主 PLL (PLL) 使能 (Main PLL (PLL) enable),0:PLL 關閉
PLLI2S:PLLI2S 使能 (PLLI2S enable),0:PLLI2S 關閉
PLLSAI:無*/
RCC->CR &= (uint32_t)0xEAF6FFFF;
/* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010;
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469_479xx) /* Reset PLLI2SCFGR register */
RCC->PLLI2SCFGR = 0x20003000;
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */
RCC->PLLSAICFGR = 0x24003000;
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ RCC->DCKCFGR = 0x00000000;
#if defined(STM32F410xx)
/* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx devices */
RCC->DCKCFGR2 = 0x00000000;
#endif /* STM32F410xx */ }
}