UVM基礎之------uvm_port_base

Port Base Classes   

uvm_port_component_base    This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase.主要用來在end_of_elaboration phase後返回某個接口的鏈接列表

uvm_port_component #(PORT)    See description of uvm_port_component_base for information about this class是對uvm_port_component_base的特化，實現uvm_port_component_base中的接口

uvm_port_base #(IF)    Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.是ports,exports,imps的基類，裏邊實例化了uvm_port_component #(PORT)

typedef uvm_port_component_base uvm_port_list[string];//定義了一個uvm_port_component_base 的數組類型uvm_port_list

uvm_port_component_base://這是一個純虛類，定義的是純虛方法，繼承自這個類的子類須要提供純虛方法的實現。

  1. 這個類定義了一個接口 在end_of_elaboration後 獲取一個端口的鏈接列表， The sub-class, uvm_port_component #(PORT), implements this interface.

  2. The connectivity lists are returned in the form of handles to objects of this type.  This allowing traversal of any port’s fan-out and fan-in network through recursive calls to get_connected_to and get_provided_to.  Each port’s full name and type name can be retrieved using get_full_name and get_type_name methods inherited from uvm_component.

  3. 內部實現的接口

   3.1 pure virtual function void get_connected_to(ref uvm_port_list list);該port被鏈接到了那些port, export,implementations,經過uvm_port_list 返回

            1. For a port or export type, this function fills list with all of the ports, exports and implementations that this port is connected to.

   3.2 pure virtual function void get_provided_to(ref uvm_port_list list);//本export,implementation爲那些port,export,implementation提供了實現

            2. For an implementation or export type, this function fills list with all of the ports, exports and implementations that this port is provides its implementation to.

   3.3 pure virtual function bit is_port();//根據本port的類型返回  

   3.4 pure virtual function bit is_export();  

   3.5 pure virtual function bit is_imp();

剖析uvm_port_component #(PORT)擴展自uvm_port_component_base

 

   2.1 惟一屬性PORT m_port;

 

   2.2 function new (string name, uvm_component parent, PORT port);給m_port=port

 

   2.3 virtual function string get_type_name()返回port的類型名字

 

   2.4 virtual function void resolve_bindings();出來m_port的全部端口連接

 

   2.5 function PORT get_port();返回m_port,下列函數都是調用m_port的對應函數實現

 

   2.6 virtual function void get_connected_to(ref uvm_port_list list);//返回實際的端口目標m_port的鏈接數

 

   2.7 virtual function void get_provided_to(ref uvm_port_list list)//返回實際的端口目標m_port的鏈接數

 

   2.8 function bit is_port ();

 

   2.9 function bit is_export ();

 

   2.10 function bit is_imp ();

uvm_port_base #(IF)該類繼承了IF並在內部組合了uvm_port_component #(PORT＝IF)而這些構成了tlm中各類接口的基類.因此uvm_port_base #(IF)是uvm_port_component #(PORT＝IF)的代理

1. 組建之間的Transaction-level 通訊是經過組件的ports，exports及imps，這些都是由這個類繼承而來。

2. IF  The interface type implemented by the subtype to this base port， For the TLM interfaces, the IF

parameter is always uvm_tlm_if_base #(T1,T2).

3.  Just before uvm_component::end_of_elaboration_phase, an internal  uvm_component::resolve_bindings process occurs， after which each port and export

holds a list of all imps connected to it via hierarchical connections to other ports and  exports

4.  uvm_port_base擁有組件的屬性,他們有一個層次實例路徑和父母    Because SystemVerilog does not support multiple inheritance, uvm_port_base cannot extend both the interface it implements and uvm_component. Thus, uvm_port_base contains a local instance of uvm_component, to which it delegates

such commands as get_name, get_full_name, and get_parent.  

// local, protected, and non-user properties

  protected int unsigned  m_if_mask;

  protected this_type     m_if;    // REMOVE

  protected int unsigned  m_def_index;

  uvm_port_component #(this_type) m_comp; //組合方式聲明一個uvm_port_component #(PORT)

  local this_type m_provided_by[string]; //鏈接到和被鏈接到的port

  local this_type m_provided_to[string];

  local uvm_port_type_e   m_port_type;

  local int               m_min_size; //容許鏈接的最大最小端口數量

  local int               m_max_size;

  local bit               m_resolved;

  local this_type         m_imp_list[string];//一個實現的列表

 

  3.1  function new (string name,

                uvm_component parent,

                uvm_port_type_e port_type,

                int min_size=0,

                int max_size=1);//配置port的類型，鏈接數的限制，等

    1. 前面兩個參數是通常的uvm_component構造類的參數

    2. The port_type can be one of UVM_PORT, UVM_EXPORT, or UVM_IMPLEMENTATION.

    3.  The min_size and max_size specify the minimum and maximum number of  implementation (imp) ports that must be connected to this port base by the end of  elaboration.  Setting max_size to UVM_UNBOUNDED_CONNECTIONS sets no maximum, i.e., an unlimited number of connections are allowed.

  3.2 function string get_name();//m_comp.get_name()

 

  3.3 virtual function string get_full_name();//m_comp.get_full_name()

 

  3.4 virtual function uvm_component get_parent()//m_comp.get_parent()

 

  3.5 virtual function uvm_port_component_base get_comp();return m_comp;

       1. 返回一個表明這個端口 內部代理組件的 句柄 

       2. Ports 被認爲是組件，可是他們並無繼承uvm_component， 相反,它們包含uvm_port_component #(PORT)的一個實例做爲這個端口的 代理

 

  3.6 virtual function string get_type_name();//返回類型名

       1.  Otherwise, only a generic 「uvm_port」, 「uvm_export」 or  「uvm_implementation」 is returned.

  3.7 function int max_size ();function int min_size ();返回大小範圍值

 

  3.8 function bit is_unbounded ();測試max_int是否無窮大，是否爲－1

 

  3.9 function bit is_port ();function bit is_export ();function bit is_imp ();測試m_port_type的類型

 

  3.10 function int size ();//返回m_imp_list.num()，鏈接到本port的export,port, implementation數

        1.  Gets the number of implementation ports connected to this port.  The value is not valid  before the end_of_elaboration phase, as port connections have not yet been resolved

  3.11function uvm_port_base #(IF) get_if(int index=0);//從m_imp_list返回一個uvm_port_base #(IF)

 

  3.12 virtual function void resolve_bindings();//該函數在end_of_elaboration phase階段前自動調用他檢查每一個port的fanout是否都提供了實現，並記下實現的數目和min, max作比較

 

  3.13 function void set_if (int index=0);//取出一個實現給m_if，m_default_if

 

  3.14 function void set_default_index (int index);

 

  3.15 local function void m_add_list           (this_type provider);把一個實現記錄到m_imp_list

 

  virtual function void connect（this type provider）；

    1. Connects this port to the given provider port，必需要知足下面的條件：

         1. Their type parameters must match

         2.  The provider’s interface type (blocking, non-blocking, analysis, etc.) must be  compatible. Each port has an interface mask that encodes the interface(s) it  supports.  If the bitwise AND of these masks is equal to the this port’s mask, the  requirement is met and the ports are compatible.  For example, a  uvm_blocking_put_port #(T) is compatible with a uvm_put_export #(T) and  uvm_blocking_put_imp #(T) because the export and imp provide the interface

required by the uvm_blocking_put_port.

        3. Ports of type UVM_EXPORT can only connect to other exports or imps.

        4.  Ports of type UVM_IMPLEMENTATION cannot be connected, as they are bound to  the component that implements the interface at time of construction

注意：

       If this port is a UVM_PORT type, the provider can be a parent port, or a sibling export or implementation port.

       If this port is a UVM_EXPORT type, the provider can be a child export or implementation port.

  3.16 local function bit  m_check_relationship (this_type provider);對鏈接關係進行檢查

 

  

   analysis port, allow connection to anywhere

 

   Connecting port-to-port: CHILD.port.connect(PARENT.port)

 

   Connecting port-to-export: SIBLING.port.connect(SIBLING.export)

   Connecting port-to-imp:    SIBLING.port.connect(SIBLING.imp)  

   Connecting export-to-export: PARENT.export.connect(CHILD.export)

   Connecting export-to-imp:    PARENT.export.connect(CHILD.imp) 

 

 3.17 function void get_provided_to (ref uvm_port_list list);  //返回m_provide_to

 

3.18function void get_connected_to (ref uvm_port_list list); //返回m_provided_by

 

 3.19function void debug_provided_to  (int level=0, int max_level=-1); //本函數打印一個port/export的圖譜

 

 3.20  function void debug_connected_to (int level=0, int max_level=-1); //本函數打印一個本port到port/export/implement的圖譜

3.21 virtual function void connect (this_type provider);//爲provider到本port提供鏈接會檢查一些鏈接規則，若是鏈接規則違反會在這裏進行告警，對這部分的鏈接規則：

 

uvm_blocking_put_port #(T)－》uvm_put_export #(T)－》uvm_blocking_put_imp #(T)

 

Ports of type <UVM_EXPORT> can only connect to other exports or imps

 

Ports of type <UVM_IMPLEMENTATION> can not be connected, as they are

  bound to the component that implements the interface at time of   

  construction.                                                     

  port is an UVM_PORT type, the ~provider~ can be a parent port,or a sibling export or implementation port

 

If this port is an <UVM_EXPORT> type, the provider can be a child export or implementation port

 

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來自爲知筆記(Wiz)