【代碼】錯誤範例

時間 2019-12-02

標籤代碼錯誤範例简体版

原文原文鏈接

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邏輯衝突優化

 1 //定義模塊輸入輸出
 2 module LED_LIGHT
 3 (
 4     input clk_in,
 5     input rst_n_in,
 6     output [7:0]led
 7 );
 8 //******************************************************
 9 parameter CLK_DIV_PERIOD = 25_000_000;//頻率25Mhz
10 
11 reg [7:0]state;
12 reg [3:0]cnt;
13 //********************************************************
14 clk_1s U1 //1s模塊
15 (
16     .clk_in(clk_in),
17     .rst_n_in(rst_n_in),
18     .clk_1s(clk_1s)
19 );
20 //************************************************************
21 always@(posedge clk_1s or negedge rst_n_in)
22 begin
23         if(!rst_n_in) 
24                 begin 
25                         state<=1'd0;
26                         cnt<=0;
27                 end
28         else
29             begin
30                 state<=state+1'b1;
31                 cnt<=cnt+1;
32                 if(cnt==8)
33                     state<=1'd0;
34             end
35 end
36 //***************************************************************
37 always@(posedge clk_in)
38 begin
39     case (state)
40         0:begin state<=8'b00000001;end
41         1:begin state<=8'b00000010;end
42         2:begin state<=8'b00000100;end
43         3:begin state<=8'b00001000;end
44         4:begin state<=8'b00010000;end
45         5:begin state<=8'b00100000;end
46         6:begin state<=8'b01000000;end
47         7:begin state<=8'b10000000;end
48         default: begin state<=8'b00000000;end
49     endcase
50 end
51 /****************************************************/
52 assign led=~state;
53     
54 endmodule
55 
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57 張慢慢  14:35:44
58 module clk_1s
59 (
60     input clk_in,
61     input rst_n_in,
62     output clk_1s
63 );
64 
65 parameter CLK_PERIOD = 25_000_000; //頻率25Mhz
66 
67 reg [25:0]cnt;
68 reg pulse;
69 
70 assign clk_1s=pulse;
71 
72 always@(posedge clk_in or negedge rst_n_in)
73     begin
74        if(!rst_n_in) 
75            cnt<=1'b0;
76         else
77             cnt<=cnt+1'b1;
78             if(cnt==(CLK_PERIOD-1))
79                 pulse<=1'b0;
80             if(cnt <(CLK_PERIOD/2)) pulse<=1'b0;
81                 else pulse<=1'b1;
82     end
83 endmodule

led_flu

 1 module clk_1s
 2 (
 3     input clk_in,
 4     input rst_n_in,
 5     output clk_1s
 6 );
 7 
 8 parameter CLK_PERIOD = 25_000_000; //頻率25Mhz
 9 
10 reg [25:0]cnt;
11 reg pulse;
12 
13 assign clk_1s=pulse;
14 
15 always@(posedge clk_in or negedge rst_n_in)
16     begin
17        if(!rst_n_in) 
18            cnt<=1'b0;
19         else
20             cnt<=cnt+1'b1;
21             if(cnt==(CLK_PERIOD-1))
22                 pulse<=1'b0;
23             if(cnt <(CLK_PERIOD/2)) pulse<=1'b0;
24                 else pulse<=1'b1;
25     end
26 endmodule

clk_1s

以上是錯誤示例，因爲語句的並行特性，會形成reg賦值時衝突，產生不肯定狀態spa

下面是優化後的代碼3d

 1 //定義模塊輸入輸出
 2 module LED_LIGHT
 3 (
 4     input clk_in,
 5     input rst_n_in,
 6     output [7:0]led
 7 );
 8 //******************************************************
 9 parameter CLK_DIV_PERIOD = 25_000_000;//頻率25Mhz
10 
11 reg [7:0]state;//一個寄存器只能在一個always內賦值
12 reg [3:0]cnt;
13 
14 wire clk_1s;
15 //********************************************************
16 clk_1s U1 //1s模塊
17 (
18     .clk_in(clk_in),
19     .rst_n_in(rst_n_in),
20     .clk_1s(clk_1s)
21 );
22 //************************************************************
23 always@(posedge clk_1s or negedge rst_n_in)
24         if(!rst_n_in) 
25             cnt<=0;    
26         else if(cnt==7)
27             cnt<=0;
28         else
29             cnt<=cnt+1'd1;
30                 
31 //***************************************************************
32 always@(posedge clk_in )
33     case (cnt)
34         0: state<=8'b00000001;
35         1: state<=8'b00000010;
36         2: state<=8'b00000100;
37         3: state<=8'b00001000;
38         4: state<=8'b00010000;
39         5: state<=8'b00100000;
40         6: state<=8'b01000000;
41         7: state<=8'b10000000;
42         default:  state<=8'b00000000;
43     endcase
44 
45 /****************************************************/
46 assign led=~state;
47     
48 endmodule

led_flu

 1 module clk_1s
 2 (
 3     input clk_in,
 4     input rst_n_in,
 5     output clk_1s
 6 );
 7 
 8 parameter CLK_PERIOD = 25_000_000; //頻率25Mhz
 9 
10 reg [25:0]cnt;
11 reg pulse;
12 
13 assign clk_1s=pulse;
14 
15 always@(posedge clk_in or negedge rst_n_in)
16     begin
17         if(!rst_n_in) 
18            cnt<=1'b0;
19         else if(cnt==(CLK_PERIOD-1))
20             begin    cnt<=1'b0; pulse<=1'b1; end
21         else
22             begin cnt<=cnt+1'b1; pulse<=1'b0; end
23             
24         
25     end
26 endmodule